(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a technique for planarization of interlevel dielectric layer.
(b) Description of the Related Art
With the advance of higher integration and higher speed of semiconductor devices, each element in the device is formed of a finer pattern. The current photolithographic technique requires a higher degree of planarization or flatness of transistor elements and overlying interlevel dielectric films for achieving the finer pattern. Examples of current planarization techniques include chemical-mechanical polishing (CMP), which however raises fabrication costs of the semiconductor device and only achieves a limited profile depending on the pattern of the interlevel dielectric film to be polished.
Patent Publication JP-A-7-37879 proposes a planarization technique for a spin-on-glass (SOG) film, formed by spin-coating of silicon oxide onto a semiconductor substrate, by using a low-temperature reflow technique, after improving the quality of the SOG silicon oxide film to be equivalent to the quality of a BPSG (borophosphosilicate glass) film by using thermal oxidation of the SOG film in a steam ambient to remove impurities in the SOG film.
The proposed technique, however, involves hardening of the SOG film itself, which may impede an effective planarity thereof.
Literature "Three "Low Dt" Options for Planarizing the Pre-metal Dielectric on an Advanced Double Poly BiCMOS Process", on Journal of Electrochemical Society, 1992, presented by W. Dauksher et al. describes a planarization technique, wherein a BPSG film comprising boron and phosphorous and formed on a transistor element is thermally treated in a steam ambient to reflow the BPSG film for planarization.
The technique of the thermal treatment of the BPSG in the steam ambient requests a temperature as high as about 800.degree. C. in the thermal treatment for obtaining a sufficient planarity because of the high melting point of the BPSG, which temperature may affect the nature of the diffused regions formed in the preceding steps to degrade the transistor characteristics.